If and case statement in vhdl

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if condition_1 then sequential statements elsif condition2 then sequential statements else sequential statements end if;

if (X = 5) and (Y = 9) then Z = 5) then Z 
process (EN, D) begin if (EN = '1') then Q 
process (ALARM_TIME, CURRENT_TIME) variable AL_EQ_CUR: boolean; begin AL_EQ_CUR := (ALARM_TIME = CURRENT_TIME); if AL_EQ_CUR then SOUND_ALARM 
process(CLK, RESET) begin if RESET = '1' then COUNT = 9) then COUNT 
case READ_CPU_STATE is when WAITING => if CPU_DATA_VALID = '1' then CPU_DATA_READ -- other branches of the case statement end case;
 
Synthesis Issues
 
 
The if statement is generally synthesisable. Where an if statement is used to detect the clock edge in a "clocked process", certain conventions must be obeyed. Using an if statement without an else clause in a "combinational process" can result in latches being inferred, unless all signals driven by the process are given unconditional default assignments. For more details see Process.
 
Whats New in '93
 
 
label: if condition then . etc end if label